Sunday, January 12, 2014

Digital Fan Regulator Circuit

The circuit presented here is that of a digital fan regulator, variable  to provide five speed levels as catered for in ordinary fan regulators. The circuit of ceiling fan controller makes use of easily available components. An optional 7-segment display with its associated electronic circuitry has been provided to display your choice of fan speed.

The heart of the circuit is a modulo-6 binary counter, built around IC2 and IC3 (IC 7476) which are dual JK flip-flops. The counter counts up in a straight binary progression from 000 to 101 (i.e. from 0 to 5) upon each successive clock edge and is reset to 000 upon next clock. The count sequence of the counter has been summarized in Table I. Each flip-flop is configured to toggle when the clock goes from high to low. 

Circuit diagram of Digital Fan Regulator : Click on image to enlarge

Let us begin with the assumption that the counter reads 000 at power on. The monoshot built around IC1 (NE 555) provides necessary pulses to trigger the counter upon every depression of switch S1. Upon the arrival of first clock edge, the counter advances to 001. The outputs of the counter go to IC4 (IC 74138), which is a 3-line to 8-line decoder. When IC4 receives the input address 001, its output Q1 goes low, while other outputs Q0 and Q2 through Q7 stay high. The output Q1, after inversion, drives transistor T1, which actuates relay RL1. Now power is delivered to the fan through the N/O contact RL1/1 of relay RL1 and the tapped resistor RT. For the tapped resistor RT, one can use the resistance found in conventional fan regulators with rotary speed regulation.

The outputs of the counter also go to IC6 (IC 7447), a BCD to 7-segment code converter, which, in turn, drives a 7-segment LED display. When switch S1 is depressed once again, the counter advances to count 010. Now, the output Q2 of IC4 goes low, while Q0, Q1 and Q3 through Q7 go high or remain high. This forces transistor T2 to saturation and actuates relay RL2. The display indicates the counter output in a 7-segment fashion.

The counter proceeds through its normal count sequence upon every depression of switch S1 up to the count 101. When switch S1 is depressed once again, normally the counter should read 110. But the two most significant bits of the counter force the output of NAND gate (IC7) to go low to reset the counter to 000. The counter now begins to count through its normal sequence all over again, upon every key depression.

The circuit does not provide the facility to memorise its previous setting once it is powered off or when there is a mains failure.

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